The present invention relates to a semiconductor device with a high breakdown voltage vertical transistor of monolithic structure provided with a clamping diode and fabricating method therefor.
For protecting a transistor from an externally applied surge current or an overvoltage induced by inductance in a switching circuit, there has been usually adopted in the art a measure to insert a clamping diode, e.g., a Zener diode between the collector and the base of the transistor.
In this instance, when the transistor to be protected is of lateral type, the clamping diode and each region of the transistor can be separated from each other. Accordingly, semiconductor devices having desired breakdown voltage characteristics in compliance with their use can be monolithically configured with ease. In contrast, in the case where the transistor to be protected is of vertical type, it is impossible to insert a clamping diode with the clamping diode and each region of the transistor separated from each other. Namely, the clamping diode is formed as a PN-junction between the collector region of the transistor and a doped region containing an opposite type dopant formed within the collector region thereof, resulting in the provision of the PN-junction with the doped region internally connected to the collector region for the transistor action. This means that the PN-junction cannot also be formed independently of regions in a lateral direction of the transistor, i.e. base and emitter regions of the transistor. Accordingly, the design of the vertical transistor is restricted by mutual interference between the PN-junction forming the clamping diode and each region of the transistor aligned in the lateral direction. For this reason, transistor devices used for high breakdown voltage cannot be monolithically configured with ease.
For instance, Japanese Patent Application Laid-open No. 57-34360 entitled "Semiconductor Device" discloses a vertical transistor wherein ion-implantation is implemented over the entire surface of the collector region to form a doped region having the same conductivity type as the collector region and a shallow depth from the surface of a semicondutor substrate so that a PN-junction is formed between the doped region and the base region adjacent thereto, thus allowing the PN-junction to serve as a clamping diode. With this vertical transistor, the breakdown voltage of the newly formed PN-junction between the doped region and the base region can be considerably lowered as compared to the breakdown voltage of a junction between the collector and the base regions of the transistor. Accordingly, in the event that an overvoltage, e.g., a surge voltage is impressed across the collector and the emitter, the PN-jucntion breakes down prior to the breakdown of the junction between the collector and the base, allowing an overcurrent to flow from the base region to ground, thus enabling the PN-junction to function as a clamping diode.
However, for the reason stated above, such a clamping diode structure is subjected to mutual interference between the PN-junction forming the clamping diode and each region of the transistor aligned in parallel, thus making it impossible to configure a transistor device for high breakdown voltage and high electric current. Assuming now that the semiconductor substrate is an N-type and the vertical transistor is of NPN structure, the clamping diode is formed by an N.sup.+ region formed in the surface of the substrate and an adjoining P-type region serving as the base. It is further assumed that a large overvoltage (e.g., 400 to 500 volts) is applied across the collector and the emitter. A large negative voltage due to the overvoltage is applied to the emitter and the overvoltage is applied to the junction of the clamping diode in a reverse direction. As a result, a large number of electrons are injected from the N.sup.+ region serving as the emitter to the P-type base region. These electrons are attracted by a strong electric field based on the overvoltage to pass through the junction of the clamping diode, eventually arriving at its N.sup.+ region. Namely, injection of a large number of positive holes from the N.sup.+ region for forming the junction of the clamping diode into the base region is initiated. Thus, the N.sup.+ region serving as the emitter, the P-type region serving as the base and the N.sup.+ region forming the junction of the clamping diode form a parasitic transistor with these regions serving as the emitter, the base and the collector, respectively. Therefore, this parasitic effect not only allows the junction of the clamping diode to secondarily break down, but also causes the transistor itself to be protected to be broken. Accordingly, with such a clamping diode structure, the fabrication of a transistor device having at most a breakdown voltage of approximately 100 volts is only possible. For the reasons stated above, monolithic high breakdown voltage vertical transistor devices with clamping diode are difficult to fabricate.